The present invention relates to a semiconductor device having a multilayer wiring structure, and more particular to a wiring method using dual Damascene technology.
In connection with the recent trend toward miniaturization of semiconductor elements, there is a demand for miniaturized wiring in the design of multilayer wiring structures for LSI. This is because the use of miniaturized wiring for the connection of the elements of LSI enables high-density element integration, provides a large number of functions for the LSI, and helps improve the performance. To meet the demand, a number of methods for forming trench wiring have been proposed.
A trench wiring forming method according to the prior art will be described with reference to FIGS. 7 through 11.
Referring first to FIG. 7, MOSFETs (101-110) are formed on a Si substrate 100 first of all. Subsequently, SiO2 111 serving as an interlayer insulating film is deposited by LP-CVD until the layer of SiO2 has a thickness of 1,000 angstroms. On the resultant structure, BPSG (Boron Phosphorous Silicate Glass) 112 also serving as an interlayer insulating film is deposited by LP-CVD until the layer of BPSG has a thickness of 10,000 angstroms. The layer of BPSG 112 is then subjected to CMP (Chemical Mechanical Polishing) in such a manner that the insulating film portions located above the source/drain diffusion layers have a thickness of 5,000 angstroms. In this manner, the rough portions which the interlayer insulating films have in accordance with the shape of gate electrodes 105 are removed, thereby providing a flat surface. The resultant structure is overlaid with an insulating film which has an etching selection ratio with reference to the BPSG (i.e., which enables selective etching by utilization of the difference in etching rates). For example, SiN 113 is deposited by LP-CVD until the layer of SiN has a thickness of 5,000 angstroms.
As shown in FIG. 8, BPSG 114 serving as an interlayer insulating film is deposited over the SiN 113 by LP-CVD until the layer of the BPSG 114 has a thickness of 3,000 angstroms. Subsequently, SiN 115 is deposited over the resultant structure by LP-CVD until the layer of the SiN 115 has a thickness of 5,000 angstroms. Thereafter, contact holes through which wires are connected to the source, drain and gate electrodes of the MOSFETs are formed by photo-etching by use of a resist pattern 116, as shown in FIG. 9. The SiN 115 is removed by anisotropic plasma etching, with the resist pattern 116 used as a mask. Then, the BPSG 114 is removed by executing anisotropic plasma etching that provides an etching selection ratio with reference to SiN.
After the resist pattern 116 is removed by ashing treatment or the like, a resist pattern 120 is formed, as shown in FIG. 10. The resist pattern 120 has a wiring pattern formed by photo-etching. Subsequently, the SiN 115 (i.e., the uppermost one of the interlayer insulating films) and the SiN 113 located at the bottom of the contact pattern are removed by anisotropic plasma etching, and the BPSG 114, 112 and the SiO2 111 directly underneath the SiN 115, 113 are removed by executing anisotropic plasma etching that provides an etching selection ratio with reference to SiN. As a result, a trench whose depth is determined by the SiN 113 is formed as a wiring pattern, and a via hole serving as a contact section is defined within the wiring trench. The Via hole leads to the gate, source and drain electrodes.
The resist pattern 120, which was used as a mask when a wiring pattern is formed, is removed by ashing treatment or the like. Subsequently, Ti/TiN are deposited by sputtering until the layer of the Ti has a thickness of 200 angstroms and the layer of the TiN has a thickness of 700 angstroms. Al heated at 300xc2x0 C. or higher is then deposited by sputtering. Since the Al maintains its fluid state when it is deposited, it flows into the via hole and the wiring pattern. Next, CMP is carried out to remove the metal portions other than the metal portions inside the wiring trench. The abrasives used in the CMP are selected from among materials that provide a selective abrasion ratio between the Al (a metal) and the SiN (i.e., materials that enables one of the Al and SiN to be selectively polished). By this CMP step, the trench wiring made of metal 117 is formed, as shown in FIG. 11. Thereafter, the process described above is repeated, and after the passivation step, an LSI is completed.
The method described above is considered to constitute the main technique of the future wiring technology. There are two reasons for this. First, in the conventional art which forms a fine wiring pattern by etching a metal layer, it is comparatively difficult to control an appropriate etching selection ratio between the wiring material and the resist, and the formation of a thin film of the resist material has come not to match the etching process. Second, in comparison with the case where wires laid out at close intervals are provided by etching a metal by using a resist pattern as a mask, the method described above enables treatment that is little affected by inclusion of dust particles or the like, and therefore enhances the manufacturing yields.
The recent progress in microstructure technology has provided more and more miniaturized elements. In addition, the wires that connect the elements are laid out at close intervals so as to arrange the elements at high density on an LSI. In other words, the adjacent wires are arranged as close as possible for high-density integration of elements. On the other hand, the distance between the wiring films, i.e., the thickness of the insulating films located between the wiring films, is not very short in comparison with the conductor spacing of wires. This is because the conductor spacing of wires is closely related with the density at which elements can be integrated on LSI chip, whereas the thickness of the insulating films between the wiring films is not. That is, the use of insulating films having a certain thickness is desirable because it helps reduce the capacitance between the wiring films and contributes a high-speed operation.
The recent progress in microstructure technology gives rise to an increase in the coupling capacitance between wires. It may be thought to use thin metal wiring films because they reduce the coupling capacitance and yet they are easy to work. At the same time, however, they result in an increase in wiring resistance and degrade the reliability in terms of the EM (electromigration). Accordingly, the characteristics of the resultant LSI are adversely affected.
As measures taken to provide a solution to the above problem, it is thought to provide a larger number of wiring films than before in such a manner that two types of wiring are formed in an LSI. To be more specific, the wiring films at a low level are made of thin films and arranged at short pitches, thereby providing local wiring. The wiring films at a high level are made of thick films and arranged at long pitches, thereby providing global wiring. That is, the higher level the wiring films are located at, the longer the wiring pitches and the thicker the wiring films are. The method that provides the above structure not only attains high-density integration but also solves the problems regarding the resistance and capacitance, and is therefore considered to improve the performance of the LSI. Due to the provision of a large number of wiring films, however, the method significantly increases the manufacturing cost and the number of defective densities, thus lowering the manufacturing yield.
The present invention has been made to solve the above problems. An object of the invention is to improve the performance of an LSI by providing thin-film wiring films in regions where micro wiring lines (such as signal lines) are required and the coupling capacitance must be reduced, and providing thick-film wiring films in regions where power/GND potentials are applied as in a wiring section (the thick-film wiring films serve to reduce the wiring resistance and suppress a voltage drop which may occur if the wiring lines are long).
To provide this object, the present invention provides a semiconductor device which has Damascene wiring formed on a semiconductor, and which is featured in that the Damascene wiring located at the same level is made of a plurality of wiring films that are different in thickness.
In the semiconductor device of the present invention, even in the same wiring film, thicknesses of wiring portions where the wiring resistance must be as low as possible, as in a power supply line and a GND line, and wiring portions where the coupling capacitance should be suppressed, as in a micro wiring pattern portion are different from each other. To be more specific, the power supply line and the GND line are made of a thick-film portion and can therefore have a reduced resistance. Hence, the performance can be enhanced without producing factors that hinder high-density integration, such as wires of increased width.
The semiconductor device of the present invention is also featured in that the wiring of the memory cell section is thinner than the same-level wiring of the peripheral circuit section. In general, a semiconductor memory does not consume much power at a memory section since the elements provided in the memory section are miniaturized so as to attain high-density integration. In contrast, the semiconductor memory requires much power at the peripheral circuit section since the elements need not be arranged at very high density and since the elements in the peripheral circuit section have to be supplied with a large amount of current for a high-speed operation. Hence, an IR drop or a voltage drop can be prevented by providing a thick wiring film in the peripheral circuit section.
In the semiconductor memory, the bit lines have to be laid out as close as possible for high element density in the memory cell section. However, the bit lines are very close to one another, they may be subject to the adverse effects caused by the coupling between adjacent bit lines. The present invention suppresses the coupling capacitance by providing a thin wiring film. It should be noted that the word lines serve to conduct a potential and cannot be easily laid out at close pitches in the memory cell section. Due to the provision of a thin wiring film, the present invention attains a reduction in the coupling capacitance between adjacent wiring lines.
The present invention provides a method for manufacturing a semiconductor device having Damascene wiring formed on a semiconductor, the method comprising the steps of: first forming an element on a semiconductor substrate, then depositing a first insulating film and flattening the first insulating film; depositing a second insulating film on the first insulating film, the second insulating film having an etching selection ratio with reference to the first insulating film; depositing third and fourth insulating films on the second insulating film, the third and fourth insulating films being formed of materials similar in kind to those of the first and second insulating films, respectively; and depositing fifth and sixth insulating films on the fourth insulating film, the fifth and sixth insulating films being formed of materials similar in kind to those of the first and second insulating films, respectively.
Subsequently, a first contact pattern is formed in a first region where a thin-film wiring film is to be formed. First resist, having a cutout pattern corresponding to the first wiring pattern, is formed in a second region where a thick-film wiring film is to be formed. With the first resist used as a mask, the sixth, fifth, fourth and third insulating films are removed by anisotropic etching in the order named.
A second wiring pattern is formed in the first region. Second resist, having a cutout pattern corresponding to the second wiring pattern, is formed in the second region. With the second resist used as a mask, the sixth and fifth insulating films are removed from the first region by etching, and the second and first insulating films are removed from the second region by etching. In concurrence therewith, the second and first insulating films are removed from the first region by etching such that they are removed in accordance with the first contact pattern.
The wiring and contact trenches formed in the first and second regions and defined by the first through sixth insulating films are filled with a metallic material. As the last step, the metallic material is removed by CMP from the regions other than the trench, with the sixth insulating film used as a stopper.
According to this method, signal lines, a power supply line, a GND line, and other wiring lines, which in the prior art are defined by a number of layers so as to provide an optimal film thickness, can be defined by a single layer. Accordingly, the performance of the semiconductor device can be remarkably improved, and the number of steps required can be significantly reduced.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.